SH7641 Datasheet, PDF (805/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 20 USB Function Module
20.3.7 USB Interrupt Enable Register 1 (USBIER1)
USBIER1 enables the interrupt requests indicated in USB interrupt flag register 1 (USBIFR1).
When an interrupt flag is set while the corresponding bit in USBIER1 is set to 1, an interrupt
request is sent to the CPU. The interrupt vector number is decided by the contents of USB
interrupt select register 1 (USBISR1).
USBIER1 is initialized to H'00 by a power-on reset.
Bit
7 to 3
Bit Name

Initial
Value
All 0
2
EP3TR
0
1
EP3TS
0
0
VBUS
0
R/W Description
R Reserved
The write value should always be 0.
R/W EP3 transfer request
R/W EP3 transmit completion
R/W USB bus connection
20.3.8 USB Interrupt Enable Register 2 (USBIER2)
USBIER2 enables the interrupt requests detected by SET_CONFIGURATION in USB interrupt
flag register 2 (USBIFR2). When the USBIFR2/SETC flag is set while the corresponding bit in
USBIER2 is set to 1, a USIHP interrupt request is sent to the CPU.
USBIER2 is initialized to H'00 by a power-on reset.
Bit
7 to 1
Bit Name

Initial
Value
All 0
0
SETC
0
R/W Description
R Reserved
The write value should always be 0.
R/W SET_CONFIGURATION request detection
Rev. 4.00 Sep. 14, 2005 Page 755 of 982
REJ09B0023-0400