SH7641 Datasheet, PDF (167/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 3 DSP Operation
3.1.8 Overflow Protection
The S bit in SR is effective for any arithmetic operations executed in the DSP unit, including the
SH's standard multiply and MAC operations. The S bit in SR, in SH's CPU core, is used as the
overflow protection enable bit. The arithmetic operation overflows when the operation result
exceeds the range of two's complement representation without guard-bit parts. Table 3.11 shows
the definition of overflow protection for fixed-point arithmetic operations, including fixed-point
signed by signed multiplication described in section 3.1.4, Fixed-Point Multiply Operation. Table
3.12 shows the definition of overflow protection for integer arithmetic operations. When an SH's
standard multiply or MAC operation is executed, the S bit function is completely the same as the
current SH CPU's definition.
When the overflow protection is effective, overflow never occurs. So, the V bit is cleared, and the
DC bit is also cleared when the overflow mode is selected by the CS[2:0] bits.
Table 3.11 Definition of Overflow Protection for Fixed-Point Arithmetic Operations
Sign
Positive
Negative
Overflow Condition
Result > 1 – 2^–31
Result < –1
Fixed Value
1 – 2^–31
–1
Hex Representation
00 7FFF FFFF
FF 8000 0000
Table 3.12 Definition of Overflow Protection for Integer Arithmetic Operations
Sign
Overflow Condition
Positive
Result > 2¹⁵ – 1
Negative
Result < –2¹⁵
Note: * means Don't care.
Fixed Value
2¹⁵ – 1
–2¹⁵
Hex Representation
00 7FFF ****
FF 8000 ****
Rev. 4.00 Sep. 14, 2005 Page 117 of 982
REJ09B0023-0400