SH7641 Datasheet, PDF (685/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
TCNT write cycle
T1
T2
Pφ
Address
TCNT_2 address
Write signal
TCNT_2
TGR2A_2 to
TGR2B_2
Ch2 compare-
match signal A/B
TCNT_1 input
clock
TCNT_1
H'FFFE
H'FFFF
N
TCNT_2 write data
H'FFFF
N+1
Disabled
M
TGRA_1
M
Ch1 compare-
match signal A
TGRB_1
Ch1 input capture
signal B
N
M
TCNT_0
P
TGRA_0 to
TGRD_0
Ch0 input capture
signal A to D
Q
P
Figure 18.79 TCNT_2 Write and Overflow/Underflow Conflict with Cascade Connection
Rev. 4.00 Sep. 14, 2005 Page 635 of 982
REJ09B0023-0400