SH7641 Datasheet, PDF (345/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value
20
MPX
0
BAS
0
19

0
18
WW2
0
17
WW1
0
16
WW0
0
15 to 13 
All 0
R/W Description
R/W MPX-IO Interface Address Wait
Specifies the address cycle insertion wait for MPX-IO
interface. This bit setting is valid only when area 5B is
specified as MPX-I/O.
0: Inserts no wait cycle
1: Inserts 1 wait cycle
R/W Byte-Selection SRAM Byte Access Selection
This bit setting is valid only when area 5B is specified
as byte-selection SRAM.
Specifies the WEn and RD/WR signal timing when the
byte-selection SRAM interface is used.
0: Asserts the WEn signal at the read timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn signal during the read access cycle
and asserts the RD/WR signal at the write timing.
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Number of Write Access Wait Cycles
R/W Specify the number of cycles that are necessary for
R/W ^{write access.}
000: The same cycles as WR[3:0] setting (number of
read access wait cycles)
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00 Sep. 14, 2005 Page 295 of 982
REJ09B0023-0400