SH7641 Datasheet, PDF (984/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 25 Electrical Characteristics
25.3.6 Burst ROM Read Cycle
CKIO
A25 to A0
CSn
RD/WR
RD
D31 to D0
T1
Tw
Twx
T2B
Twb
T2B
t_AD1
t_AD2
t_AD2
t_AD1
t_CSD1 t_AS
t_CSD1
t_RWD1
t_RSD
t_RWD1
t_RDS3
t_RSD
t_RDH3
t_RDS3
t_RDH3
WEn
BS
DACKn,
TENDn*
WAIT
t_BSD
t_BSD
t_DACD
t_WTH1
t_WTH1
t_WTS1
t_WTS1
t_DACD
Note: * Waveform for DACKn and TENDn when active low is selected.
Figure 25.22 Burst ROM Read Cycle
(One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two Burst)
Rev. 4.00 Sep. 14, 2005 Page 934 of 982
REJ09B0023-0400