SH7641 Datasheet, PDF (132/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
2.6.2 Added CPU System Control Instructions
The new instructions in this class are treated as part of the CPU core functions, and therefore all
the added instructions have a 16-bit code length. All the additional instructions belong to the
system control instruction group. Table 2.25 summarizes the added system instructions. New
control registers—RS, RE, and MOD—have been added to the CPU core to support loop control
and modulo addressing functions, and LDC and STS type instructions have been provided for
these registers.
The DSP engine's DSR, A0, X0, X1, Y0, and Y1 registers are treated as system registers such as
MACH and MACL, and therefore STS and LDS instructions are supported for these registers. As
digital signal processing operations usually employ a multi-level nested-loop structure, DSP
performance can be improved by means of a zero-overhead loop control function. SETRC type
instructions are provided to set the repeat count in the RC field in SR[27:16]. When an immediate
operand type SETRC instruction is executed, the 8-bit immediate operand data is set in SR[23:16],
and 0 is set in the remaining bits, SR[27:24]. When a register operand type SETRC instruction is
executed, Rn[11:0] is set in SR[27:16]. The start address and end address of the repeat loop are set
in the RS register and RE register. There are two ways of setting the addresses: by using an LDC
type instruction, or by using the LDRS and LDRE instructions.
Table 2.25 Added CPU System Control Instructions
Instruction
Instruction Code
SETRC #imm
10000010iiiiiiii
SETRC Rn
0100nnnn00010100
LDRS @(disp,PC) 10001100dddddddd
LDRE @(disp,PC) 10001110dddddddd
STC MOD,Rn
0000nnnn01010010
STC RS,Rn
0000nnnn01100010
STC RE,Rn
0000nnnn01110010
STS DSR,Rn
0000nnnn01101010
STS A0,Rn
0000nnnn01111010
STS X0,Rn
0000nnnn10001010
STS X1,Rn
0000nnnn10011010
STS Y0,Rn
0000nnnn10101010
STS Y1,Rn
0000nnnn10111010
Operation
imm → RC (of SR)
Rn[11:0] → R C (of SR)
(disp × 2 + PC) → RS
(disp × 2 + PC) → RE
MOD → Rn
RS → Rn
RE → Rn
DSR → Rn
A0 → Rn
X0 → Rn
X1 → Rn
Y0 → Rn
Y1 → Rn
Execution
States T Bit
1

1

1

1

1

1

1

1

1

1

1

1

1

Rev. 4.00 Sep. 14, 2005 Page 82 of 982
REJ09B0023-0400