SH7641 Datasheet, PDF (268/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 9 Exception Handling
9.6 Usage Notes
1. An instruction assigned at a delay slot of the RTE instruction is executed after the contents of
the SSR is restored into the SR. An acceptance of an exception related to instruction access is
determined according to the SR before restore. An acceptance of other exceptions is
determined by the SR after restore, processing mode, and BL bit value. A processing-
completion type exception is accepted before an instruction at the RTE branch destination
address is executed. However, note that the correct operation cannot be guaranteed if a re-
execution type exception occurs.
2. In an instruction assigned at a delay slot of the RTE instruction, a user break cannot be
accepted.
3. If the BL bit of the SR register is changed by the LDC instruction, an exception is accepted
according to the changed SR value from the next instruction.* A processing-completion type
exception is accepted before the next instruction is executed. An interrupt and DMA address
error in re-execution type exceptions are accepted before the next instruction is executed.
Note: * If an LDC instruction is executed for the SR, the following instructions are re-fetched
and an instruction fetch exception is accepted according to the modified SR value.
Rev. 4.00 Sep. 14, 2005 Page 218 of 982
REJ09B0023-0400