SH7641 Datasheet, PDF (1020/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Appendix
[Legend]
I: Input
I+: Input with weak keeper
I++: Input with pull-up MOS
O: Output
L: Low level output
H: High level output
Z: Hi-Z (The pin must not be open since the intermediate level at this pin caused a pass though
current in the LSI.)
Z+: Hi-Z with weak keeper
Z++: Hi-Z with pull-up MOS
K: Input becomes Hi-Z, output retains state
Notes: 1. The EXTAL pin must be pulled up and the XTAL pin must be open.
2. Controlled by the HIZCNT bit in the common control register of the BSC.
3. Controlled by the HIZMEM bit in the common control register of the BSC.
4. Controlled by the HIZ bit in the standby control register.
5. The pin must not be open since the intermediate level at this pin causes the path
though current in the LSI.
6. The data register of the I/O port can be written to.
7. Hi-Z when the TAP controller of the H-UDI is neither Shift-DR nor Shift-IR state.
8. When the H-UDI is not used, pins ASEMD0, TCK, TDI, and TMS must be pulled up, the
TDO and ASEBRKAK pins must be open, and the TRST pin must be connected to the
RESETP pin or ground.
For use of emulators, the board must be designed following instructions in the emulator
manual.
Rev. 4.00 Sep. 14, 2005 Page 970 of 982
REJ09B0023-0400