SH7641 Datasheet, PDF (494/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 13 Direct Memory Access Controller (DMAC)
13.4.6 Completion of DMA Transfer
The conditions for the completion of DMA transfer differ according to whether we are considering
completion of transfer on individual channels or simultaneous completion of transfer on all
channels.
1. Conditions for the completion of transfer on individual channels
Either of the following events indicates the completion of transfer on the corresponding
channel.
 The value in the DMA transfer count register (TCR) becomes 0.
 The DMA enable bit (DE) in the DMA channel control register (CHCR) becomes 0.
A. Completion of transfer indicated by TCR = 0
The TCR value becomes 0 when the DMA transfer on the corresponding channel has been
completed, and the transfer-end bit flag (TE) is set to indicate this. In this case, if the
interrupt enable bit (IE) has been set, a DMAC interrupt (DEI) request is sent to the CPU.
When transferring data in 16-byte units, specify a number of transfers, as for transfers with
other transfer-units.
B. Completion of transfer indicated by DE = 0 in CHCR
Clearing of the DMA enable bit (DE) of CHCR halts DMA transfer on the corresponding
channel. In this case, the TE bit is not set.
2. Concurrent completion of transfer on all channels:
Either of the following events indicates the concurrent completion of transfer on all channels.
 The NMI flag bit (NMIF) or address error flag bit (AE) of the DMA operation register
becomes 1.
 The DMA master enable bit (DME) of DMAOR becomes 0.
A. Completion of transfer indicated by NMIF = 1 or AE = 1 in DMAOR
When an NMI interrupt is generated or the DMAC generates an address error and the
NMIF bit or AE bit of DMAOR is set to 1, DMA transfer on all channels is suspended. The
contents of the DMA source address register (SAR), the DMA destination register (DAR),
and the DMA transfer count register (TCR) are updated (including that of the channel on
which the address error occurred) by the transfer immediately before the suspension. If the
transfer is the final transfer, TE becomes 1 and the transfer is then completed. If an address
error is generated during transfer in the dual address mode, pay attention on the following
points.
Rev. 4.00 Sep. 14, 2005 Page 444 of 982
REJ09B0023-0400