SH7641 Datasheet, PDF (110/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Instruction Format
Source
Operand
Destination
Operand
Sample Instruction
d type
dddddddd: GBR R0 (register direct) MOV.L @(disp,GBR),R0
15
0 ^{indirect with}
xxxx xxxx dddd dddd
displacement
R0 (register direct) dddddddd: GBR
indirect with
displacement
MOV.L
@R0,@(disp,GBR)
dddddddd:
PC-relative with
displacement
R0 (register direct) MOVA @(disp,PC),R0
dddddddd:

PC-relative
BF
label
d12 type
15
dddddddddddd: 
0 ^PC-relative
xxxx dddd dddd dddd
BRA label
(label=disp+PC)
nd8 type
dddddddd: PC-
15
0 ^{relative with}
xxxx nnnn dddd dddd
displacement
nnnn: register
direct
MOV.L @(disp,PC),Rn
i type
15
iiiiiiii:
0 ^immediate
xxxx xxxx i i i i i i i i
Indexed GBR
indirect
AND.B
#imm,@(R0,GBR)
iiiiiiii:
immediate
iiiiiiii:
immediate
ni type
15
iiiiiiii:
0 ^immediate
xxxx nnnn i i i i i i i i
R0 (register direct) AND #imm,R0

TRAPA #imm
nnnn: register
direct
ADD #imm,Rn
Rev. 4.00 Sep. 14, 2005 Page 60 of 982
REJ09B0023-0400