SH7641 Datasheet, PDF (599/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
Initial
Bit
Bit Name value R/W Description
3
TGIED
0
R/W TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channels 0, 3, and 4.
In channels 1 and 2, bit 3 is reserved. It is always read
as 0, and should only be written with 0.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
2
TGIEC
0
R/W TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in
channels 0, 3, and 4.
In channels 1 and 2, bit 2 is reserved. It is always read
as 0, and should only be written with 0.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
1
TGIEB
0
R/W TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
0
TGIEA
0
R/W TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit and DMA transfer when the TGFA bit in TSR
is set to 1.
0: Interrupt requests (TGIA) by TGFA bit and DMA
transfer disabled
1: Interrupt requests (TGIA) by TGFA bit and DMA
transfer enabled
Note: Do not change the setting of the timer interrupt enable register (TIER) during DMA transfer.
Rev. 4.00 Sep. 14, 2005 Page 549 of 982
REJ09B0023-0400