SH7641 Datasheet, PDF (551/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 16 I²C Bus Interface 2 (IIC2)
16.4.7 Noise Filter
The logic levels at the SCL and SDA pins are routed through noise filters before being latched
internally. Figure 16.17 shows a block diagram of the noise filter circuit.
The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the system clock. When NF2CYC is set to 0, this signal is not passed forward
to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this signal is
not passed forward to the next circuit unless the outputs of three latches agree. If they do not
agree, the previous value is held.
Sampling clock
SCL or SDA
input signal
C
D
Q
Latch
C
D
Q
Latch
C
D
Q
Latch
Match
detector
Sampling
clock
Peripheral clock
cycle
Match
detector
NF2CVC
Figure 16.17 Block Diagram of Noise Filter
1
Internal
SCL or SDA
signal
0
Rev. 4.00 Sep. 14, 2005 Page 501 of 982
REJ09B0023-0400