SH7641 Datasheet, PDF (820/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 20 USB Function Module
Data Stage (Control-IN): The application first analyzes command data from the host in the setup
stage, and determines the subsequent data stage direction. If the result of command data analysis is
that the data stage is in-transfer, one packet of data to be sent to the host is written to the FIFO. If
there is more data to be sent, this data is written to the FIFO after the data written first has been
sent to the host (USBIFR0/EP0iTS = 1).
The end of the data stage is identified when the host transmits an OUT token and the status stage
is entered.
USB function
IN token reception
Application
From setup stage
1 written
to USBTRG/EP0s
RDFN?
Yes
No
NACK
Valid data
in EP0i FIFO?
Yes
No
NACK
Data transmission to host
ACK
Set EP0i transmission
complete flag
(USBIFR0/EP0i TS = 1)
Interrupt request
Write data to USBEP0i
data register (USBEPDR0i)
Write 1 to EP0i packet
enable bit
(USBTRG/EP0i PKTE = 1)
Clear EP0i transmission
complete flag
(USBIFR0/EP0i TS = 0)
Write data to USBEP0i
data register (USBEPDR0i)
Write 1 to EP0i packet
enable bit
(USBTRG/EP0i PKTE = 1)
Figure 20.6 Data Stage (Control-IN) Operation
Note:
If the size of the data transmitted by the function is smaller than the data size requested by
the host, the function indicates the end of the data stage by returning to the host a packet
shorter than the maximum packet size. If the size of the data transmitted by the function is
an integral multiple of the maximum packet size, the function indicates the end of the data
stage by transmitting a zero-length packet.
Rev. 4.00 Sep. 14, 2005 Page 770 of 982
REJ09B0023-0400