SH7641 Datasheet, PDF (804/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 20 USB Function Module
20.3.5 USB Interrupt Select Register 1 (USBISR1)
USBISR1 selects the vector numbers of the interrupt requests indicated in USB interrupt flag
register 1 (USBIFR1). If the USB issues an interrupt request to the INTC when the corresponding
bit in USBISR1 is cleared to 0, the interrupt will be USI0 (USB interrupt 0). If the USB issues an
interrupt request to the INTC when the corresponding bit in USBISR1 is set to 1, the interrupt will
be USI1 (USB interrupt 1). If interrupts occur simultaneously, USI0 has priority by default.
USBISR1 is initialized to H'07 by a power-on reset.
Bit
7 to 3
Bit Name

Initial
Value
All 0
2
EP3TR
0
1
EP3TS
0
0
VBUSF
0
R/W Description
R Reserved
The write value should always be 0.
R/W EP3 transfer request
R/W EP3 transmission completion
R/W USB bus connection
20.3.6 USB Interrupt Enable Register 0 (USBIER0)
USBIER0 enables the interrupt requests indicated in USB interrupt flag register 0 (USBIFR0).
When an interrupt flag is set while the corresponding bit in USBIER0 is set to 1, an interrupt
request is sent to the CPU. The interrupt vector number is decided by the contents of USB
interrupt select register 0 (USBISR0).
USBIER0 is initialized to H'00 by a power-on reset.
Initial
Bit
Bit Name Value
R/W Description
7
BRST
0
R/W Bus reset
6
EP1FULL 0
R/W EP1FIFO full
5
EP2TR
0
R/W EP2 transfer request
4
EP2EMPTY 0
R/W EP2 FIFO empty
3
SETUPTS 0
R/W Setup command receive completion
2
EP0oTS
0
R/W EPOo receive completion
1
EP0iTR
0
R/W EPOi transfer request
0
EP0iTS
0
R/W EPOi transmit completion
Rev. 4.00 Sep. 14, 2005 Page 754 of 982
REJ09B0023-0400