SH7641 Datasheet, PDF (109/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Instruction Format
Source
Operand
Destination
Operand
Sample Instruction
nm type
15
xxxx
nnnn
mmmm
0
xxxx
md type
15
xxxx xxxx
mmmm
0
dddd
mmmm: register
direct
nnnn: register
direct
ADD Rm,Rn
mmmm: register
direct
nnnn: register
indirect
MOV.L Rm,@Rn
mmmm: post-
increment register
indirect (multiply-
and-accumulate
operation)
MACH, MACL
MAC.W @Rm+,@Rn+
nnnn: * post-
increment register
indirect (multiply-
and-accumulate
operation)
mmmm: post-
nnnn: register
increment register direct
indirect
MOV.L @Rm+,Rn
mmmm: register
direct
nnnn: pre-
MOV.L Rm,@-Rn
decrement register
indirect
mmmm: register
direct
nnnn: indexed
register indirect
MOV.L Rm,@(R0,Rn)
mmmmdddd:
R0 (register direct) MOV.B @(disp,Rm),R0
register indirect
with displacement
nd4 type
R0 (register direct) nnnndddd:
MOV.B R0,@(disp,Rn)
15
xxxx
xxxx
nnnn
0
dddd
register indirect
with displacement
nmd type
15
xxxx
nnnn mmmm
0
dddd
mmmm: register
direct
nnnndddd:
MOV.L Rm,@(disp,Rn)
register indirect
with displacement
mmmmdddd:
nnnn: register
register indirect direct
with displacement
MOV.L @(disp,Rm),Rn
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Rev. 4.00 Sep. 14, 2005 Page 59 of 982
REJ09B0023-0400