SH7641 Datasheet, PDF (108/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
2.4.3 CPU Instruction Formats
Table 2.13 shows the instruction formats, and the meaning of the source and destination operands,
for instructions executed by the CPU core. The meaning of the operands depends on the
instruction code. The following symbols are used in the table.
xxxx: Instruction code
mmmm: Source register
nnnn: Destination register
iiii:
Immediate data
dddd: Displacement
Table 2.13 CPU Instruction Formats
Instruction Format
Source
Operand
Destination
Operand
Sample Instruction
0 type


NOP
15
xxxx xxxx
xxxx
0
xxxx
n type
15
xxxx
nnnn

xxxx
0
xxxx
nnnn: register
direct
MOV T Rn
m type
15
xxxx mmmm xxxx
0
xxxx
Control register or nnnn: register
system register direct
STS MACH,Rn
Control register or nnnn: pre-
STC.L SR,@-Rn
system register decrement register
indirect
mmmm: register
direct
Control register or LDC
system register
Rm,SR
mmmm: post-
Control register or LDC.L @Rm+,SR
increment register system register
indirect
mmmm: register

indirect
JMP @Rm
PC-relative using 
Rm
BRAF Rm
Rev. 4.00 Sep. 14, 2005 Page 58 of 982
REJ09B0023-0400