SH7641 Datasheet, PDF (755/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
1
RDF
0
R/(W)* Receive FIFO Data Full
Indicates that receive data has been transferred to the
receive FIFO data register (SCFRDR), and the
quantity of data in SCFRDR has become more than
the receive trigger number specified by the RTRG1
and RTRG0 bits in the FIFO control register
(SCFCR).
0: The quantity of transmit data written to SCFRDR is
less than the specified receive trigger number
[Clearing conditions]
• RDF is cleared to 0 by a power-on reset, standby
mode
• RDF is cleared to 0 when the SCFRDR is read
until the quantity of receive data in SCFRDR
becomes less than the specified receive trigger
number after 1 is read from RDF and then 0 is
written
• RDF is cleared to 0 when DMAC read SCFRDR
until the quantity of receive data in SCFRDR
becomes less than the specified receive trigger
number
1: The quantity of receive data in SCFRDR is more
than the specified receive trigger number
[Setting condition]
• RDF is set to 1 when a quantity of receive data
more than the specified receive trigger number is
stored in SCFRDR*
Note: * SCFTDR is a 16-byte FIFO register. When
RDF is 1, the specified receive trigger
number of data can be read. If an attempt is
made to read after all the data in SCFRDR
has been read, the data is undefined. The
quantity of receive data in SCFRDR is
indicated by the lower 8 bits of SCFDR.
Rev. 4.00 Sep. 14, 2005 Page 705 of 982
REJ09B0023-0400