SH7641 Datasheet, PDF (249/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 9 Exception Handling
9.1.2 Exception Event Register (EXPEVT)
EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception
codes to be specified in EXPEVT are those for resets and general exceptions. These exception
codes are automatically specified the hardware when an exception occurs. Only bits 11 to 0 of
EXPEVT can be re-written using the software.
Initial
Bit
Bit Name Value R/W Description
31 to 12 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0 EXPEVT *
R/W 12-Bit Exception Code
Note: * Initialized to H'000 at power-on reset and H'020 at manual reset.
9.1.3 Interrupt Event Register 2 (INTEVT2)
INTEVT2 is assigned to address H'A4000000 and consists of a 12-bit exception code. Exception
codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are
automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified
using the software.
Initial
Bit
Bit Name Value R/W Description
31 to 12 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0 INTEVT2 
R/W 12-Bit Exception Code
Note: Initialized to H'000 at power-on reset and H'020 at manual reset.
Rev. 4.00 Sep. 14, 2005 Page 199 of 982
REJ09B0023-0400