SH7641 Datasheet, PDF (242/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 7 Cache
7.4.3 Usage Examples
Invalidating Specific Entries
Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory mapping
cache access. When the A bit is 1, the address tag specified by the write data is compared to the
address tag within the cache selected by the entry address, and data is written to the bits V and U
specified by the write data when a match is found. If no match is found, there is no operation.
When the V bit of an entry in the address array is set to 0, the entry is written back if the entry's U
bit is 1.
An example when a write data is specified in R0 and an address is specified in R1 is shown below.
; R0=H'0110 0000; tag address=B'0000 0001 0001 0000 0000 00, U=0, V=0
; R1=H'F000 0088; address array access, entry=B'00001000, A=1
;
MOV.L R0,@R1
Reading the Data of a Specific Entry
The data section of a specific cache entry can be read by the memory mapping cache access. The
longword indicated in the data field of the data array in figure 7.4 is read into the register.
An Example when an address is specified in R0 and data is read in R1.
; R0=H'F100 004C; data array access, entry=B'00000100,
; Way=0, longword address=3
;
MOV.L @R0,R1 ; Longword 3 is read.
Rev. 4.00 Sep. 14, 2005 Page 192 of 982
REJ09B0023-0400