SH7641 Datasheet, PDF (538/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 16 I²C Bus Interface 2 (IIC2)
16.4 Operation
The I²C bus interface can communicate either in I²C bus mode or clocked synchronous serial mode
by setting FS in SAR.
16.4.1 I²C Bus Format
Figure 16.3 shows the I²C bus formats. Figure 16.4 shows the I²C bus timing. The first frame
following a start condition always consists of eight bits.
(a) I²C bus format (FS = 0)
S
SLA
R/W A
1
7
11
1
DATA
n
A
1
m
A/A P
11
n: Transfer bit count (n = 1 to 8)
m: Transfer frame count (m ≥ 1)
(b) I²C bus format (Start condition retransmission, FS = 0)
S
SLA
R/W A
DATA
1
7
11
n1
A/A S
11
1
m1
SLA
R/W A
7
11
1
DATA
n2
m2
A/A P
11
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
Figure 16.3 I²C Bus Formats
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
SLA R/W A
DATA
A
DATA
Figure 16.4 I²C Bus Timing
A
P
Rev. 4.00 Sep. 14, 2005 Page 488 of 982
REJ09B0023-0400