SH7641 Datasheet, PDF (159/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 3 DSP Operation
3.1.5 Shift Operations
Shift operations can use either register or immediate value as the shift amount operand. Other
source and destination operands are specified by the register. There are two kinds of shift
operations. Table 3.7 shows the variation of this type of operation. The correspondence between
each operand and registers, except for immediate operands, is the same as the ALU fixed-point
operations as shown in table 3.2.
Table 3.7 Variation of Shift Operations
Mnemonic
Function
Source 1
PSHA Sx, Sy, Dz Arithmetic shift
Sx
PSHL Sx, Sy, Dz Logical shift
Sx
PSHA #Imm1, Dz Arithmetic shift with
Dz
immediate.
PSHL #Imm2, Dz Logical shift with
Dz
immediate.
Note: –32 <= Imm1 <= +32, –16 <= Imm2 <= +16
Source 2
Sy
Sy
Imm1
Imm2
Destination
Dz
Dz
Dz
Dz
Arithmetic Shift: Figure 3.9 shows the arithmetic shift operation flow.
7g 0g 31
Left Shift
16 15
0
0
Shift out
7g
Shift amount data:
(Source 2)
Ignored
>=0
<0
0g 31
+32 to –32
23 22 16 15
Sy
60
Imm1
7g 0g 31
(MSB copy)
Right Shift
16 15
0
Shift out
0
Updated GT Z N V DC
DSR
Figure 3.9 Arithmetic Shift Operation Flow
Note:
The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the
base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit
parts when a register not providing the guard-bit parts is specified as the source operand.
When a register not providing the guard-bit parts is specified as a destination operand, the
lower 32 bits of the operation result are input into the destination register.
Rev. 4.00 Sep. 14, 2005 Page 109 of 982
REJ09B0023-0400