SH7641 Datasheet, PDF (729/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
Output Level Control/Status Register (OCSR): OCSR is a 16-bit readable/writable register that
controls the enable/disable of both output level comparison and interrupts, and indicates status. If
the OSF bit is set to 1, the high current pins become high impedance.
Bit
Bit Name
15
OSF
14 to 10 
Initial
value
0
All 0
R/W Description
R/(W)* Output Short Flag
This flag indicates that any one pair of the three pairs
of 2 phase outputs compared have simultaneously
become low level outputs.
[Clear condition]
• By writing 0 to OSF after reading an OSF = 1
[Set condition]
• When any one pair of the three 2-phase outputs
simultaneously become low level
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00 Sep. 14, 2005 Page 679 of 982
REJ09B0023-0400