SH7641 Datasheet, PDF (46/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Table 12.10
Table 12.11
Table 12.11
Table 12.12
Table 12.12
Table 12.13
Table 12.13
Table 12.14
Table 12.15
Table 12.16
Table 12.17
Table 12.18
Table 12.19
Table 12.20
Table 12.21
Table 12.22
Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (3)........................................................................... 344
Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (4)-1........................................................................ 345
Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (4)-2........................................................................ 346
Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (5)-1........................................................................ 347
Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (5)-2........................................................................ 348
Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (6)-1........................................................................ 349
Relationship between BSZ1, 0, A2/3ROW1, 0, and
Address Multiplex Output (6)-2........................................................................ 350
Relationship between Access Size and Number of Bursts................................ 351
Access Address in SDRAM Mode Register Write ........................................... 371
Output Addresses when EMRS Command Is Issued........................................ 374
Relationship between Bus Width, Access Size, and Number of Bursts............ 376
Minimum Number of Idle Cycles between
CPU Access Cycles for the Normal Space Interface ........................................ 389
Minimum Number of Idle Cycles between Access Cycles during
DMAC Dual Address Mode Transfer for the Normal Space Interface............. 390
Minimum Number of Idle Cycles during DMAC Single Address Mode
Transfer to the Normal Space Interface from the
External Device with DACK ............................................................................ 391
Minimum Number of Idle Cycles between Access Cycles of CPU and
the DMAC Dual Address Mode for the SDRAM Interface.............................. 393
Minimum Number of Idle Cycles between Access Cycles of
the DMAC Single Address Mode for the SDRAM Interface ........................... 396
Section 13 Direct Memory Access Controller (DMAC)
Table 13.1 Pin Configuration.................................................................................................. 407
Table 13.2 Combination of the Round-Robin Select Bits and Priority Mode Bits ................. 420
Table 13.3 Transfer Request Module/Register ID .................................................................. 423
Table 13.4 Selecting External Request Modes with the RS Bits ............................................ 426
Table 13.5 Selecting External Request Detection with Dl, DS Bits ....................................... 427
Table 13.6 Selecting External Request Detection with DO Bit .............................................. 427
Table 13.7 Selecting On-Chip Peripheral Module Request Modes with
the RS3 to RS0 Bits .............................................................................................. 428
Table 13.8 Supported DMA Transfers.................................................................................... 432
Table 13.9 Relationship of Request Modes and Bus Modes by DMA Transfer Category ..... 439
Rev. 4.00 Sep. 14, 2005 Page xlvi of l