SH7641 Datasheet, PDF (852/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 21 A/D Converter
Initial
Bit
Bit Name Value R/W Description
14
ADIE
0
R/W A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested at the
end of A/D conversion. Set the ADIE bit while A/D
conversion is not being made.
0: A/D end interrupt request (ADI) is disabled
1: A/D end interrupt request (ADI) is enabled
13
ADST
0
R/W A/D Start
Starts or stops A/D conversion. The ADST bit remains
set to 1 during A/D conversion.
0: A/D conversion is stopped
1: A/D conversion is started
Single mode: A/D conversion starts; ADST is
automatically cleared to 0 when conversion ends on
all selected channels
Multi mode: A/D conversion starts; when conversion is
completed cycling through the selected channels,
ADST is automatically cleared
Scan mode: A/D conversion starts and continues, A/D
conversion is continuously performed until ADST is
cleared to 0 by software, by a power-on reset, or by a
transition to standby mode
12
DMASL 0
R/W DMAC Select
Selects an interrupt due to the end of A/D conversion or
activation of the DMAC. Set the DMASL bit while A/D
conversion is not being made.
0: An interrupt by the end of A/D conversion is selected
1: Activation of the DMAC by the end of A/D conversion
is selected
11
TRGE
0
R/W A/D Trigger Enable
This bit enables or disables starting of A/D conversion by
MTU or CSL trigger.
0: Start of A/D conversion by MTU or CSL trigger input is
disabled
1: A/D conversion is started MTU or CSL trigger input
Rev. 4.00 Sep. 14, 2005 Page 802 of 982
REJ09B0023-0400