SH7641 Datasheet, PDF (125/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Instruction
Instruction Code
Operation
Execution
States
T Bit
SUBV Rm,Rn
0011nnnnmmmm1011 Rn–Rm → Rn, Underflow → T 1
Underflow
Notes: 1. The normal minimum number of execution cycles is two, but five cycles are required
when the operation result is read from the MAC register immediately after the
instruction.
2. The normal minimum number of execution cycles is one, but three cycles are required
when the operation result is read from the MAC register immediately after the MUL
instruction.
Logic Operation Instructions
Table 2.21 Logic Operation Instructions
Instruction
AND
Rm,Rn
AND
#imm,R0
AND.B #imm,@(R0,GBR)
Instruction Code
0010nnnnmmmm1001
11001001iiiiiiii
11001101iiiiiiii
NOT
OR
OR
OR.B
Rm,Rn
Rm,Rn
#imm,R0
#imm,@(R0,GBR)
0110nnnnmmmm0111
0010nnnnmmmm1011
11001011iiiiiiii
11001111iiiiiiii
TAS.B @Rn
0100nnnn00011011
TST
Rm,Rn
0010nnnnmmmm1000
TST
#imm,R0
11001000iiiiiiii
TST.B #imm,@(R0,GBR) 11001100iiiiiiii
XOR
XOR
XOR.B
Rm,Rn
#imm,R0
#imm,@(R0,GBR)
0010nnnnmmmm1010
11001010iiiiiiii
11001110iiiiiiii
Operation
Rn & Rm → Rn
R0 & imm → R0
(R0 + GBR) & imm →
(R0 + GBR)
~Rm → Rn
Rn | Rm → Rn
R0 | imm → R0
(R0 + GBR) | imm →
(R0 + GBR)
If (Rn) is 0, 1 → T;
1 → MSB of (Rn)
Rn & Rm; if the result
is 0, 1 → T
R0 & imm; if the result
is 0, 1 → T
(R0 + GBR) & imm;
if the result is 0, 1 → T
Rn ^ Rm → Rn
R0 ^ imm → R0
(R0 + GBR) ^ imm →
(R0 + GBR)
Execution
States
T Bit
1
—
1
—
3
—
1
—
1
—
1
—
3
—
4
Test
result
1
Test
result
1
Test
result
3
Test
result
1
—
1
—
3
—
Rev. 4.00 Sep. 14, 2005 Page 75 of 982
REJ09B0023-0400