SH7641 Datasheet, PDF (765/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
7
RTRG1
0
R/W Receive FIFO Data Trigger
6
RTRG0
0
R/W Set the quantity of receive data which sets the receive
data full (RDF) flag in the serial status register
(SCFSR). The RDF flag is set when the quantity of
receive data stored in the receive FIFO register
(SCFRDR) is increased more than the set trigger
number shown below.
• Asynchronous mode • Synchronous mode
00: 1
00: 1
01: 4
10: 8
11: 14
01: 2
10: 8
11: 14
5
TTRG1
0
R/W Transmit FIFO Data Trigger 1, 0
4
TTRG0
0
R/W Set the quantity of remaining transmit data which sets
the transmit FIFO data register empty (TDFE) flag in the
serial status register (SCFSR). The TDFE flag is set
when the quantity of transmit data in the transmit FIFO
data register (SCFTDR) becomes less than the set
trigger number shown below.
00: 8 (8)*
01: 4 (12)*
10: 2 (14)*
11: 0 (16)*
Note: * Values in parentheses mean the number of
empty bytes in SCFTDR when the TDFE flag is
set to 1.
3
MCE
0
R/W Modem Control Enable
Enables modem control signals CTS and RTS.
In synchronous mode, MCE bit should always be 0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * CTS is fixed at active 0 regardless of the input
value, and RTS is also fixed at 0.
Rev. 4.00 Sep. 14, 2005 Page 715 of 982
REJ09B0023-0400