SH7641 Datasheet, PDF (907/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 23 I/O Ports
23.7.2 Port G Data Register (PGDR)
PGDR a register that includes six readable/writable and eight readable bits with two reserved bits
that store data for pins PTG13 to PTG0.
PGDR13 to PGDR8 are initialized to H'00 by a power-on reset, but they retain their previous
values by a manual reset, in standby mode, or in sleep mode. PGDR7 to PGDR0 are not initialized
by a power-on or manual reset, in standby mode, or in sleep mode. (The bit always indicates the
status of the pin.)
Initial
Bit
Bit Name Value R/W Description
15, 14 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
13
PG13DT 0
12
PG12DT 0
11
PG11DT 0
10
PG10DT 0
R/W Bits PG13DT to PG8DT correspond to pins PTG13 to
R/W ^{PTG8. When the function is general input port, the}
corresponding pin level is read by reading the port.
R/W _{Tables 23.8 and 23.9 show the function of PGDRs 13}
R/W ^{to 8.}
9
PG9DT
0
R/W
8
PG8DT
0
R/W
7
PG7DT
0
R/W Bits PG7DT to PG0DT correspond to pins PTG7 to
6
PG6DT
0
R/W ^{PTG0. The values written to these bits are ignored and}
does not affect pin state. If these bits are read, the
5
PG5DT
0
R/W _{states of the pins are returned directly instead of the}
4
PG4DT
0
R/W ^{values of these bits. Do not read these bits when the}
A/D converter is used. Table 23.10 shows the function
3
PG3DT
0
R/W _{of PGDR.}
2
PG2DT
0
R/W
1
PG1DT
0
R/W
0
PG0DT
0
R/W
Note: * The initial value depends on the status of the pin at reading.
Rev. 4.00 Sep. 14, 2005 Page 857 of 982
REJ09B0023-0400