SH7641 Datasheet, PDF (94/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
2.2.3 Memory Data Formats
Memory data formats are classified into byte, word, and longword. Byte data can be accessed
from any address, but an address error will occur if word data starting from an address other than
2n or longword data starting from an address other than 4n is accessed. In such cases, the data
accessed cannot be guaranteed (figure 2.11).
Address A
Address A + 4
Address A + 8
Address A + 1 Address A + 3
Address A
Address A + 2
31
23
15
7
0
Byte 0 Byte 1 Byte 2 Byte 3
Word 0
Word 1
Longword
Big-endian mode
Figure 2.11 Byte, Word, and Longword Alignment
2.3 Features of CPU Core Instructions
The CPU core instructions are RISC-type instructions with the following features:
Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code
efficiency.
One Instruction per State: Pipelining is used, and basic instructions can be executed in one state.
Data Size: The basic data size for operations is longword. Byte, word, or longword can be
selected as the memory access size. Memory byte or word data is sign-extended and operated on
as longword data. Immediate data is sign-extended to longword size for arithmetic operations or
zero-extended to longword size for logical operations.
Rev. 4.00 Sep. 14, 2005 Page 44 of 982
REJ09B0023-0400