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SH7641 Datasheet, PDF (757/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series | |||
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.3.8 Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.
Each channel has independent baud rate generator control, so different values can be set in three
channels.
The SCBRR setting is calculated as follows:
⢠Asynchronous mode:
N=
PÏ
à 106 - 1
64 Ã 22n-1 Ã B
⢠Synchronous mode:
N=
8Ã
PÏ
22n-1 Ã B
Ã
106
-1
B: Bit rate (bits/s)
N: SCBRR setting for baud rate generator (0 ⤠N ⤠255)
PÏ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 19.2.)
Table 19.2 SCSMR Settings
SCSMR Settings
n
Clock Source
CKS1
CKS0
0
PÏ
0
0
1
PÏ/4
0
1
2
PÏ/16
1
0
3
PÏ/64
1
1
Note: The bit rate error in asynchronous is given by the following formula:
Error (%) =
PÏ Ã 106
- 1 Ã 100
(N + 1) Ã B Ã 642n-1 Ã 2
Rev. 4.00 Sep. 14, 2005 Page 707 of 982
REJ09B0023-0400
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