SH7641 Datasheet, PDF (134/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
2.6.3 Single and Double Data Transfer for DSP Data Instructions
The new instructions in this class are provided to reduce the program code size for DSP
operations. All the new instructions in this class have a 16-bit code length. Instructions in this
class are divided into two groups: single data transfer instructions and double data transfer
instructions. The double data-transfer instructions provide the same flexibility in operand specification as is
provided by the A fields of the data-transfer instruction fields of parallel-processing instructions. This is
described in section 2.4.4, DSP Instruction Formats. Conditional load instructions cannot be used with
these 16-bit instructions. In single transfer, the Ax pointer and two other pointers are used as the
As pointer, but the Ay pointer is not used. Tables 2.26 and 2.27 list the single and double data
transfer instructions.
With double data transfer group instructions, X memory and Y memory can be accessed in
parallel. The Ax pointer can only be used by X memory access instructions, and the Ay pointer
only by Y memory access instructions. Double data transfer instructions can only access the on-
chip X and Y memory areas. Single data transfer instructions use a 16-bit instruction code, and
can access any memory address space.
Rn (n = 2 to 7) registers are normally used as the Ax, Ay, and As pointers. The pointer names
themselves can be changed with the assembler rename function. The following renaming scheme
is recommended.
R2:As2, R3:As3, R4:Ax0 (As0), R5:Ax1 (As1), R6:Ay0, R7:Ay1, R8:Ix, R9:Iy
Rev. 4.00 Sep. 14, 2005 Page 84 of 982
REJ09B0023-0400