SH7641 Datasheet, PDF (994/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 25 Electrical Characteristics
CKIO
Td1 Td2 Td3 Td4
Tc1 Tc2 Tc3 Tc4
Tde
t_AD1
t_AD1
t_AD1
A25 to A0
Column
address
t_AD1
A12/A11*¹
t_AD1
Read command
CSn
RD/WR
RASU/L
CASU/L
DQMxx
t_CSD1
t_RWD1
t_RASD1
t_CASD1
t_DQMD1
t_CSD1
t_RWD1
t_CASD1
t_DQMD1
D31 to D0
t_BSD
BS
t_RDS2 t_RDH2
t_BSD
t_RDS2 t_RDH2
CKE
DACKn*²
t_DACD
(High)
t_DACD
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, WTRCD = 0 Cycle)
Rev. 4.00 Sep. 14, 2005 Page 944 of 982
REJ09B0023-0400