SH7641 Datasheet, PDF (146/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Table 2.32 DC Bit Update Definitions
CS [2:0] Condition Mode Description
0 0 0 Carry or borrow
mode
The DC bit is set if an ALU arithmetic operation generates a carry
or borrow, and is cleared otherwise.
When a PSHA or PSHL shift instruction is executed, the last bit
data shifted out is copied into the DC bit.
When an ALU logical operation is executed, the DC bit is always
cleared.
0 0 1 Negative value
mode
When an ALU or shift (PSHA) arithmetic operation is executed,
the MSB of the result, including the guard bits, is copied into the
DC bit.
When an ALU or shift (PSHL) logical operation is executed, the
MSB of the result, excluding the guard bits, is copied into the DC
bit.
0 1 0 Zero value mode The DC bit is set if the result of an ALU or shift operation is all-
zeros, and is cleared otherwise.
0 1 1 Overflow mode
The DC bit is set if the result of an ALU or shift (PSHA) arithmetic
operation exceeds the destination register range, excluding the
guard bits, and is cleared otherwise.
When an ALU or shift (PSHL) logical operation is executed, the
DC bit is always cleared.
1 0 0 Signed greater-than This mode is similar to signed greater-or-equal mode, but DC is
mode
cleared if the result is all-zeros.
DC = ~{(negative value ^ over-range) | zero value};
In case of arithmetic operation
DC = 0; In case of logical operation
1 0 1 Signed greater-or-
equal mode
If the result of an ALU or shift (PSHA) arithmetic operation
exceeds the destination register range, including the guard bits
("over-range"), the definition is the same as in negative value
mode. If the result is not over-range, the definition is the opposite
of that in negative value mode.
When an ALU or shift (PSHL) logical operation is executed, the
DC bit is always cleared.
DC = ~(negative value ^ over-range);
In case of arithmetic operation
DC = 0 ; In case of logical operation
1 1 0 Reserved
1 1 1 Reserved
Rev. 4.00 Sep. 14, 2005 Page 96 of 982
REJ09B0023-0400