SH7641 Datasheet, PDF (103/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
R8[Ix]
+2 (INC)
+0 (no update)
R4[Ax]
R5[Ax]
R9[Iy]
+2 (INC)
+0 (no update)
R6[Ay]
R7[Ay]
ALU
AU
[Legend]
AU: Adder provided for DSP addressing
Note:
Three address processing methods:
1. Increment
2. Index register addition (Ix/Iy)
3. No increment
Post-updating is used in all cases.
The address pointer can be decremented by setting in the index register.
Figure 2.12 X and Y Data Transfer Addressing
Single Data Addressing: DSP instructions include two single data transfer instructions
(MOVS.W and MOVS.L) that load data into, or store data from, a DSP register. With these
instructions, one of registers R2 to R5 is used as the single data transfer address register (As).
The following four kinds of addressing can be used with single data transfer instructions.
1. Non-update address register addressing:
The As register is an address pointer. It is not updated.
2. Addition index register addressing:
The As register is an address pointer. After a data transfer, the value of the Is register is added
to the As register (post-increment).
3. Increment address register addressing:
The As register is an address pointer. After a data transfer, the As register is incremented by 2
or 4 (post-increment).
4. Decrement address register addressing:
The As register is an address pointer. Before a data transfer, –2 or –4 is added to the As
register (i.e. 2 or 4 is subtracted) (pre-decrement).
Rev. 4.00 Sep. 14, 2005 Page 53 of 982
REJ09B0023-0400