SH7641 Datasheet, PDF (258/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 9 Exception Handling
Unconditional trap:
• Conditions
TRAPA instruction executed
• Types
Instruction synchronous, processing-completion type
• Save address
An address of an instruction following TRAPA
• Exception code
H'160
• Remarks
The exception is a processing-completion type, so PC of the instruction after the TRAPA
instruction is saved to SPC. The 8-bit immediate value in the TRAPA instruction is quadrupled
and set in TRA9 to TRA0.
User break point trap:
• Conditions
When a break condition set in the user break controller is satisfied
• Types
Break (L bus) before instruction execution: Instruction synchronous, re-execution type
Operand break (L bus): Instruction synchronous, processing-completion type
Data break (L bus): Instruction asynchronous, processing-completion type
I bus break: Instruction asynchronous, processing-completion type
• Save address
Re-execution type: An address of the instruction where a break occurs (a delayed branch
instruction address if an instruction is assigned to a delay slot)
Operand break (L bus): An address of the instruction following the instruction where a break
occurs (a delayed branch instruction destination address if an instruction is assigned to a delay
slot)
Data break (L bus): Instruction asynchronous, processing-completion type
• Exception code
H'1E0
• Remarks
For details on user break controller, refer to section 11, User Break Controller (UBC).
Rev. 4.00 Sep. 14, 2005 Page 208 of 982
REJ09B0023-0400