SH7641 Datasheet, PDF (537/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 16 I²C Bus Interface 2 (IIC2)
16.3.7 I²C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible.
16.3.8 I²C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot write to this register.
16.3.9 I²C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the
CPU.
16.3.10 NF2CYC Register (NF2CYC)
NF2CYC is an 8-bit readable/writable register that selects the range of the noise filtering for the
SCL and SDA pins. For details of the noise filter, see section 16.4.7, Noise Filter.
NF2CYC is initialized to H'00 by a power-on reset.
Bit
7 to 1
0
Bit Name

NF2CYC
Initial
Value
All 0
0
R/W Description
R Reserved
These bits are always read as 0.
R/W Noise Filtering Range Select
0: The noise less than one cycle of the peripheral clock
can be filtered out
1: The noise less than two cycles of the peripheral clock
can be filtered out
Rev. 4.00 Sep. 14, 2005 Page 487 of 982
REJ09B0023-0400