SH7641 Datasheet, PDF (333/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
21
IWRRD2 1
R/W Idle Cycles for Read-Read in Another Space
20
WRRD1
1
19
IWRRD0 1
R/W Specify the number of idle cycles to be inserted after
R/W ^{the access to a memory that is connected to the}
space. The target cycle is a read-read cycle of which
continuous accesses switch between different spaces.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
18
IWRRS2 1
R/W Idle Cycles for Read-Read in the Same Space
17
IWRRS1 1
16
IWRRS0 1
R/W Specify the number of idle cycles to be inserted after
R/W ^{the access to a memory that is connected to the}
space. The target cycle is a read-read cycle of which
continuous accesses are for the same space.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
15

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 4.00 Sep. 14, 2005 Page 283 of 982
REJ09B0023-0400