SH7641 Datasheet, PDF (190/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 3 DSP Operation
Input/output
control for
DSP data
registers
X0/X1, A0/A1
Instruction code for X
data-transfer operation
Control
for X memory
31
0 31
0
R4 [Ax]
R6 [Ay]
R5 [Ax]
R7 [Ay]
15
1
ABx
15
1
ABy
XAB 16-bit
Instruction code for Y
data-transfer operation
Control
for Y memory
Input/output
control for
DSP data
registers
Y0/Y1, A0/A1
X_MEM
X R/W
YAB 16-bit
X data
memory
4 kbytes
Y data
memory
4 kbytes
Y_MEM
Y R/W
XDB
YDB
X_MEM and Y_MEM:
Select X and Y data memory
16-bit
16-bit
Figure 3.22 Load/Store Control for X and Y Data-Transfer Instructions
Control for X Memory:
if ( !Nop ) {
X_MEM=1; XAB=ABx;
if ( load operation ) {
Dx[31:16]=XDB;
Dx[15:0]=0x0000;
}
else XDB = Dx[31:16];
}
else { X_MEM=0; XAB=0x000; }
/* Dx is X0 or X1 */
/* Dx is A0 or A1 */
The conditional execution based on the DC flag in DSR cannot control any MOVX/MOVY
instructions.
Rev. 4.00 Sep. 14, 2005 Page 140 of 982
REJ09B0023-0400