SH7641 Datasheet, PDF (163/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 3 DSP Operation
Every time a PDMSB operation is executed, the DC, N, Z, V, and GT bits in DSR are basically
updated in accordance with the operation result. In case of a conditional operation, they are not
updated, even though the specified condition is true, and the operation is executed. In case of an
unconditional operation, they are always updated with the operation result.
39 31
0
Guard
Source 1 or 2
Priority encoder
GT Z N V DC
DSR
Guard Destination
39 31
Cleared
0
Figure 3.11 PDMSB Operation Flow
The definition of the DC bit is selected by the CS0 to CS2 (condition selection) bits in DSR. The
DC bit result is:
1. Carry or Borrow Mode: CS[2:0] = 000
The DC bit is always cleared.
2. Negative Value Mode: CS[2:0] = 001
The DC bit is set when the operation result is a negative value, and cleared when the operation
result is zero or a positive value.
3. Zero Value Mode: CS[2:0] = 010
The DC bit is set when the operation result is zero; otherwise it is cleared.
4. Overflow Mode: CS[2:0] = 011
The DC bit is always cleared.
5. Signed Greater Than Mode: CS[2:0] = 100
The DC bit is set when the operation result is a positive value; otherwise it is cleared.
6. Signed Greater Than or Equal Mode: CS[2:0] = 101
The DC bit is set when the operation result is zero or a positive value; otherwise it is cleared.
Rev. 4.00 Sep. 14, 2005 Page 113 of 982
REJ09B0023-0400