SH7641 Datasheet, PDF (851/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Table 21.2 Analog Input Channels and A/D Data Registers
Analog Input Channel
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
A/D Data Register
ADDRA0
ADDRB0
ADDRC0
ADDRD0
ADDRA1
ADDRB1
ADDRC1
ADDRD1
Module
A/D0
A/D1
Section 21 A/D Converter
21.2.2 A/D Control/Status Registers (ADCSR0, ADCSR1)
ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter,
and enable or disable starting of A/D conversion by external trigger input.
ADCSR is initialized to H'0040 by a power-on reset and in standby mode.
Initial
Bit
Bit Name Value R/W Description
15
ADF
0
R/(W)* A/D End Flag
Indicates the end of A/D conversion.
[Clearing conditions]
• Cleared by reading ADF while ADF = 1, then
writing 0 to ADF
• Cleared when DMAC is activated by ADI interrupt
and ADDR is read
[Setting conditions]
• Single mode: A/D conversion ends
• Multi mode: A/D conversion ends cycling through
the selected channels
• Scan mode: A/D conversion ends cycling through
the selected channels
Rev. 4.00 Sep. 14, 2005 Page 801 of 982
REJ09B0023-0400