SH7641 Datasheet, PDF (689/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
Pφ
TCNT input
clock
TCNT
Counter clear
signal
TGF
TCFV
H'FFFF
Disabled
H'0000
Figure 18.83 Conflict between Overflow and Counter Clearing
18.7.17 Conflict between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 18.84 shows the operation timing when there is conflict between TCNT write and
overflow.
TCNT write cycle
T1
T2
Pφ
Address
TCNT address
Write signal
TCNT
TCFV flag
H'FFFF
TCNT write data
M
Figure 18.84 Conflict between TCNT Write and Overflow
Rev. 4.00 Sep. 14, 2005 Page 639 of 982
REJ09B0023-0400