SH7641 Datasheet, PDF (679/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.5 Conflict between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 18.72 shows the timing in this case.
TCNT write cycle
T1
T2
Pφ
Address
TCNT address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 18.72 Conflict between TCNT Write and Increment Operations
Rev. 4.00 Sep. 14, 2005 Page 629 of 982
REJ09B0023-0400