SH7641 Datasheet, PDF (788/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
• Receiving Serial Data (Synchronous Mode)
Figure 19.15 shows a sample flowchart for receiving serial data. When switching from
asynchronous mode to synchronous mode without SCIF initialization, make sure that ORER, PER,
and FER are cleared to 0.
Start of reception
Read ORER flag in SCLSR
ORER = 1?
No
Read RDF flag in SCFSR
Yes
[1]
Error handling
[2]
[1] Receive error handling:
Read the ORER flag in SCLSR to
identify any error, perform the appropriate
error handling, then clear the ORER flag
to 0. Reception cannot be resumed while
the ORER flag is set to 1.
[2] SCIF status check and receive data read:
Read SCFSR and check that RDF = 1,
then read the receive data in SCFRDR,
and clear the RDF flag to 0. The transition
of the RDF flag from 0 to 1 can also be
identified by an RXI interrupt.
No
RDF = 1?
Yes
Read receive data in
SCFRDR, and clear RDF
[3]
flag in SCFSR to 0
No
All data received?
Yes
[3] Serial reception continuation procedure:
To continue serial reception, read at least
the receive trigger set number of receive
data bytes from SCFRDR, read 1 from the
RDF flag, then clear the RDF flag to 0.
The number of receive data bytes in
SCFRDR can be ascertained by reading
SCFRDR.
However RDF bits is cleared to 0
automatically when the data in SCFRDR
is read out by the DMAC.
Clear RE bit in SCSCR to 0
End of reception
Figure 19.15 Sample Flowchart for Receiving Serial Data (1)
Rev. 4.00 Sep. 14, 2005 Page 738 of 982
REJ09B0023-0400