SH7641 Datasheet, PDF (259/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 9 Exception Handling
DMA address error:
• Conditions
 Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
 Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
4n + 3)
• Types
Instruction synchronous, processing-completion type
• Save address
An address of the instruction following the instruction where a break occurs (a delayed branch
instruction destination address if an instruction is assigned to a delay slot)
• Exception code
H'5C0
• Remarks
An exception occurs when a DMA transfer is executed while an illegal instruction address
described above is specified in the DMAC. Since the DMA transfer is performed
asynchronously with the CPU instruction operation, an exception is also requested
asynchronously with the instruction execution. For details on DMAC, refer to section 13,
Direct Memory Access Controller (DMAC).
Rev. 4.00 Sep. 14, 2005 Page 209 of 982
REJ09B0023-0400