SH7641 Datasheet, PDF (211/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 5 Watchdog Timer (WDT)
5.3.4 Using Interval Timer Mode
When operating in interval timer mode, interval timer interrupts are generated at every overflow of
the counter. This enables interrupts to be generated at set periods.
1. Clear the WT/IT bit in the WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits,
and set the initial value of the counter in the WTCNT.
2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF in WTCSR to 1 and an interval timer
interrupt request is sent to INTC. The counter then resumes counting.
5.4 Precautions to Take when Using the WDT
Pay attention to the following points when using the WDT in either the interval timer or watchdog
timer mode.
1. Timer tolerance
After timer operation has started, the period from the power-on reset point to the first count up
timing of the WTCNT varies depending on the time period that is set by the TME bit of the
WTCSR register. The shortest such time period is thus one cycle of the peripheral clock, pφ,
while the longest is the result of frequency division according to the value in CKS2 to CKS0.
The timing of subsequent incrementation is in accord with the selected frequency divisor. This
time difference is referred to as timer variation. This also applies to the timing of the first
incrementation after the WTCNT register has been written to during timer operation.
2. Do not set WTCNT to H'FF
When the value in WTCNT reaches H'FF, the WDT assumes that an overflow has occurred.
Accordingly, when H'FF is placed in WTCNT, an interval timer interrupt or WDT reset will
occur immediately, regardless of the current clock selection by bits CKS2 to CKS0.
Rev. 4.00 Sep. 14, 2005 Page 161 of 982
REJ09B0023-0400