SH7641 Datasheet, PDF (562/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 17 Compare Match Timer (CMT)
Initial
Bit
Bit Name value R/W Description
1
CKS1
0
R/W Clock Select
0
CKS0
0
R/W These bits select the clock to be input to CMCNT from
four internal clocks obtained by dividing the peripheral
operating clock (Pφ). When the STR bit in CMSTR is
set to 1, CMCNT starts counting on the clock selected
with bits CKS1 and CKS0.
00: Pφ/4
01: Pφ/8
10: Pφ/16
11: Pφ/64
Note: * Only 0 can be written, to clear the flag.
17.2.3 Compare Match Counter (CMCNT )
CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with
bits CKS1 and CKS0 in CMCSR, and the STR bit in CMSTR is set to 1, CMCNT starts counting
using the selected clock.
When the value in CMCNT and the value in compare match constant register (CMCOR) match,
CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1.
CMCNT is initialized to H'0000 by a power on reset, but is not initialized in standby mode.
17.2.4 Compare Match Constant Register (CMCOR)
CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT.
CMCOR is initialized to H'FFFF by a power on reset, but is not initialized in standby mode.
Rev. 4.00 Sep. 14, 2005 Page 512 of 982
REJ09B0023-0400