SH7641 Datasheet, PDF (894/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 23 I/O Ports
23.1.2 Port A Data Register (PADR)
PADR is a 15-bit readable/writable register with one reserved bit that stores data for pins PTA14
to PTA0. PADR is initialized to H'0000 by a power-on reset, but it retains its previous value by a
manual reset, in standby mode or in sleep mode.
Initial
Bit
Bit Name Value R/W Description
15

0
R Reserved
This bit is always read as 0. The write value should
always be 0.
14
PA14DT 0
13
PA13DT 0
12
PA12DT 0
11
PA11DT 0
10
PA10DT 0
9
PA9DT
0
R/W Bits PA14DT to PA0DT correspond to pins PTA14 to
R/W ^{PTA0. When the pin function is general output port, the}
value of the corresponding PADR bit in PADR is
R/W _{returned directly by reading the port. When the function}
R/W ^{is general input port, the corresponding pin level is read}
by reading the port. Table 23.1 shows the function of
R/W _PADR.
R/W
8
PA8DT
0
R/W
7
PA7DT
0
R/W
6
PA6DT
0
R/W
5
PA5DT
0
R/W
4
PA4DT
0
R/W
3
PA3DT
0
R/W
2
PA2DT
0
R/W
1
PA1DT
0
R/W
0
PA0DT
0
R/W
Rev. 4.00 Sep. 14, 2005 Page 844 of 982
REJ09B0023-0400