SH7641 Datasheet, PDF (256/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 9 Exception Handling
Table 9.2 Type of Reset
Type
Condition to reset
Power-on reset RESETP = Low level
Manual reset RESETM = Low level
H-UDI reset
H-UDI reset command entry
Internal state
CPU
On-chip peripheral module
Initialization Refer to the register
configurations in the relevant
sections.
9.3.2 General Exceptions
CPU address error:
• Conditions
 Instruction is fetched from odd address (4n + 1, 4n + 3)
 Word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3)
 Long word is accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
4n + 3)
 The area ranging from H'80000000 to H'FFFFFFFF in logical space is accessed in user
mode
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'0E0
An exception occurred during write: H'1E0
• Remarks
None
Rev. 4.00 Sep. 14, 2005 Page 206 of 982
REJ09B0023-0400