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| SH7641 Datasheet, PDF (1000/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series | |||
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Section 25 Electrical Characteristics
CKIO
A25 to A0
A12/A11*1
CSn
RD/WR
RASU/L
CASU/L
Tp
Tpw
Trr
Trc
tAD1
tAD1
tAD1
tAD1
tCSD1
tCSD1
tCSD1
tCSD1
tRWD1
tRWD1
tRASD1
tRASD1
tRASD1
tRASD1
tCASD1
tCASD1
Trc
Trc
Trc
tRWD1
DQMxx
D31 to D0
(Hi-Z)*3
BS
CKE
tCKED1
tCKED1
DACKn*2
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
3. Pins D31 to D16 with weak keeper are retained as weak keepers.
Figure 25.38 Synchronous DRAM Self-Refreshing Timing
(WTRP = 1 Cycle)
Rev. 4.00 Sep. 14, 2005 Page 950 of 982
REJ09B0023-0400
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