SH7641 Datasheet, PDF (812/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 20 USB Function Module
Initial
Bit
Bit Name Value R/W Description
0
EP0iCLR 0
W
EP0i Clear
When 1 is written to this bit, the endpoint 0 transmit
FIFO buffer is initialized.
20.3.20 USBDMA Transfer Setting Register (USBDMAR)
USBDMAR enables DMA transfer between the endpoint 1 and endpoint 2 data registers and
memory by means of the on-chip DMA controller (DMAC). Dual address transfer is performed
with the transfer size of only on a per-byte basis. In order to start DMA transfer, DMAC settings
must be made in addition to the settings in this register. For details of DMA transfer, see
section 20.7, DMA Transfer.
USBDMAR can be initialized to H'00 by a power-on reset.
Bit
7 to 2
Bit Name

Initial
Value
All 0
1
EP2DMAE 0
R/W Description
R Reserved
The write value should always be 0.
R/W Endpoint 2 DMA Transfer Enable
When this bit is set, DMA transfer is enabled from
memory to the endpoint 2 transmit FIFO buffer. If
there is at least one byte of space in the FIFO buffer,
a transfer request is asserted for the DMA controller.
In DMA transfer, when 64 bytes are written to the
FIFO buffer, the EP2 packet enable bit is set
automatically, allowing 64 bytes of data to be
transferred. If there is still space in the other of the
two FIFOs, a transfer request is asserted for the DMA
controller again. However, if the size of the data
packet to be transmitted is less than 64 bytes, the
EP2 packet enable bit is not set automatically, and so
should be set by the CPU with a DMA transfer end
interrupt.
Also, as EP2-related interrupt requests to the CPU
are not automatically masked, interrupt requests
should be masked as necessary in the interrupt
enable register.
Rev. 4.00 Sep. 14, 2005 Page 762 of 982
REJ09B0023-0400