SH7641 Datasheet, PDF (371/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
12.5 Operating Description
12.5.1 Endian/Access Size and Data Alignment
This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the
byte data.
Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byte-
selection SRAM. Two data bus width (16 bits and 32 bits) are available for SDRAM. Data bus
width for MPX-IO is fixed to 32 bits. Data alignment is performed in accordance with the data bus
width of the device. This also means that when longword data is read from a byte-width device,
the read operation must be done four times. In this LSI, data alignment and conversion of data
length is performed automatically between the respective interfaces.
Table 12.5 through 12.7 show the relationship between device data width and access unit.
Table 12.5 32-Bit External Device Access and Data Alignment
Data Bus
Operation
D31 to
D24
D23 to
D16
D15 to
WE3,
D8
D7 to D0 DQMUU
Byte access
Data

at 0
7 to 0


Assert
Byte access

Data



at 1
7 to 0
Byte access

at 2

Data


7 to 0
Byte access

at 3


Data

7 to 0
Word access Data
Data

at 0
15 to 8
7 to 0

Assert
Word access

at 2

Data
Data

15 to 8 7 to 0
Longword
access at 0
Data
31 to 24
Data
23 to 16
Data
15 to 8
Data
7 to 0
Assert
Strobe Signals
WE2,
DQMUL
WE1,
DQMLU


Assert


Assert


Assert


Assert
Assert
Assert
WE0,
DQMLL



Assert

Assert
Assert
Rev. 4.00 Sep. 14, 2005 Page 321 of 982
REJ09B0023-0400